1. Technical Field
The present invention relates to the planarizing of a substrate surface during electronic device processing.
2. Background Information
Integrated circuits have been formed in a planarized fashion on silicon substrates for many years. The integrated circuit has rapidly decreased in size and the number of devices that are formed on the silicon wafer number in the millions. The diameters of the silicon wafers have continued to increase from the 50 mm wafers in the 1960s to the 200 mm and 300 mm wafers that are common on the IC fabrication lines today.
As the wafers increased in size, the manufacturing problems became more complex. The processing techniques that were engineered for 200 mm wafer tools are now used to process the 300 mm wafers. Problems, such as temperature non-uniformities across the surface of a wafer, are much more difficult to control on 300 mm wafers with techniques developed for 200 mm wafers that present less than half the surface area.
Such temperature non-uniformities present film non-uniformities that are deposited across the surface of the wafer. A temperature variation of just 5 degrees Celsius may deposit material at different growth rates in localized areas on the wafer. Growth characteristics are not only related to temperature but may be effected by other parameters such as growth chamber pressure, cracking efficiency of the source materials, diffusion coefficients of the individual constituents of the species, and the vapor pressure of the reactants.
Many deposition processes occur in reactors using susceptors that rotate during deposition. The rotating susceptor alleviates gross non-uniform deposition patterns on the substrate. However, the non-uniformities still exist but are less severe and the patterns are generally rotational. Many deposition processes leave a thicker pattern on the outer edge of the wafer.
For instance, many processes are performed in a horizontal reactor where the gases pass across the wafer. As the gases flow across the wafer, the source material cracks and deposits material forming the film and depleting the carrier gas of source material. Thus, the growth rate slows as the gas flows across the wafer. Therefore, the growth rate for the film is highest at the leading edge of the substrate and lowest at the trailing edge. Rotating the wafer tends to offset the depletion effects of the source material by rotating the wafer through the varying growth rates making the average growth rate across the wafer much more uniform. However, it is difficult to match the rotation of the wafer to the exact growth rate in any one area of the wafer. Therefore, the thickest areas of the film in a horizontal reactor may occur at the outside radius of the substrate.
As the line-widths of electronic devices become smaller, the photo-lithographic processes that form the masking layers for defining the line-widths may require shorter wavelengths of light to properly expose the photo-resist. Photolithography is a process used for defining a pattern on a wafer using wavelengths in the ultraviolet wavelength range. Since film non-uniformities demonstrate a material of varying thickness across the surface of the wafer, the focusing of the light to properly expose the photo-resist becomes difficult. As the film thickness changes across the wafer so do the focal points for the photolithography process, resulting in poorly-formed line-widths.
Since the deposition of materials may leave a textured surface, techniques such as chemical-mechanical polishing (“CMP”) have been developed to planarize the surface of the wafer. For the most part, CMP has resolved the depth of focus problem for the photo-lithographic processes. However, not all exposed materials are etched and polished at the same rate during the CMP process. Some materials are harder than others, resisting both the mechanical polishing and etching thus leaving features with residual layer material.